Locality: Bengaluru Area, India
Summary: ASIC, FPGA RTL Design, Validation in domains like Ethernet, USB2.0, 802.11 a,b,g, SONET, SDH, VME
Past: Consultant at CG CoreEl Lead Design Engg at Conexant Lead Design Engg at Paxonet Communications see less...
Education: C-DAC. Pune (1999-2000)
Nagpur University Electronics (1996-1999)
Experience: CG CoreEl (Privately Held; Design industry): Consultant, (December 2007-April 2009)
Conexant (Public Company; CNXT; Semiconductors industry): Lead Design Engg, (December 2004-August 2007)
Paxonet Communications (Semiconductors industry): Lead Design Engg, (April 2000-December 2004)
Interests: career opportunities, consulting offers, new ventures, job inquiries, expertise requests, business deals, reference requests, getting back in touch
... engg mechanics not changed b.e.e. not changed 3 515 f.e.(sem-i) vadali jyotsna sanyasirao b ... f.e.(sem-i) bhoye dinesh laxman computer prog - inot changed 19 6357 f.e.(sem-i) gaidhani ...
... 70.16% RAVANDALE SARIKA BHANUDAS Female Semester 20416 DSE1018605 304 40 70.13% GAIDHANI MITHILA ... 76.06% MANKAR VEENA BHARAT Female Semester 11410 DSE1005508 302 3 75.45% HAKE JYOTSNA YUVRAJ Female ...
Prof. Dolly wattal dhar: New Delhi - 110012 ... Ms. JYOTSNA JOTSHI: PUNE - 411004 ... Ms. Sharvari Gaidhani: Pune - 411007
a b c d e f g; 1: nameof_the candidate: rollno: centre: post1: post2: post3: post4: 2: abdul gaffar khan: 1314090756: nagpur: jr eng (dist) trainee : 3 : abdul jaleel: 1205092335
SUPREME COURT OF INDIA CAUSE LIST (For 05th, September, 2008 )
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