Vishwas Kudlu

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Vishwas Kudlu
Vishwas Kudlu

Locality: Bengaluru Area, India
Summary: Over 8 years of experience in ASIC/FPGA RTL front end design using verilog/VHDL. 1. Worked with networking protocols like Ethernet, EPON 2. Worked with communication protocols like USB3.0 and PCIe 3. Knowledge of Interface like OCP 4. Complete FPGA design cycle knowledge, from design to PAR and bitfile loading onto board. And on-board testing of complex SoC prototypes. 5. Basic knowledge of Synopsys-DC
Past: Senior R&D Engineer at Agilent Technologies Design Engineer at Wipro Technologies
Education:  Mangalore University Electronics and Communication (1997-2001) 
 Kendriya Vidyalaya   
 Nanyang Technological University   

Industry: Semiconductors
Skills: Ethernet, EPON, USB3.0, PCIe, OCP frontend RTL design with verilog and VHDL. FPGA and ASIC flow. System architecture development
Experience: CANON INDIA PVT. LTD (Privately Held; Information Technology and Services industry): Team Lead,  (2008-Present) Working with FPGA and ASIC frontend RTL design on cutting-edge communication protocols.
Agilent Technologies (Public Company; A; Electrical/Electronic Manufacturing industry): Senior R&D Engineer,  (2005-2008) Handheld Ethernet LAN testing...
Interests: career opportunities, consulting offers, new ventures, job inquiries, expertise requests, business deals, reference requests, getting back in touch

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