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Jaynarayan Tudu, E Larsson, V Singh, and V D Agrawal Proc. of European Test Symposium, 2009. Capture Power Reduction for Moduler System-on-Chip Test
"Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation", Pramod Subramanyan, Ram Rakesh Jangir, Jaynarayan Tudu, Erik Larsson and Virendra ...
Jaynarayan Tudu: jaynarayan004@gmail.com, jayttudu@csa.iisc.ernet.in . Or . Pawan Kumar: er.pawan@gmail.com, pawan@rishi.serc.iisc.ernet.in
Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, `Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach`, 15 th IEEE ...
Jaynarayan Tudu, E Larsson, V Singh, and V D Agrawal Proc. of European Test Symposium, 2009. Capture Power Reduction for Moduler System-on-Chip Test
"Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation", Pramod Subramanyan, Ram Rakesh Jangir, Jaynarayan Tudu, Erik Larsson and ...
Jaynarayan Tudu: jaynarayan004@gmail.com, jayttudu@csa.iisc.ernet.in . Or . Pawan Kumar: er.pawan@gmail.com, pawan@rishi.serc.iisc.ernet.in
Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, `Scan cell reordering .... Jaynarayan Tudu (with Prof. Matthew Jacob); Pramod Subramanyan ...
Jaynarayan Tudu, E Larsson, V Singh, and V D Agrawal ... Pramod Subramanyan ...
Jaynarayan Tudu, Erik Larsson, and Virendra Singh, `Test Scheduling of ...
Bengaluru Area, India - Student at iiscView jaynarayan Tudu's (India) professional profile on LinkedIn. LinkedIn is the world's largest business network, helping professionals like jaynarayan ...
India - --View jaynarayan tudu's (India) professional profile on LinkedIn. LinkedIn is ...
2009 European Test Symposium On Minimization of Peak Power for Scan Circuit during Test (2010) · Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, ...
DBLP keys, 2010. 3, Electronic Edition · pubzone.org · CiteSeerX · Google scholar · BibTeX · bibliographical record in XML, Jaynarayan T. Tudu, Erik Larsson ...
[3], Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara. Graph theoretic approach for scan cell reordering to minimize peak shift power. ...
Scan circuit generally causes excessive switching activitycompared to normal circuit operation. The higher switchingactivity in turn causes higher peak ...
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