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Power Delay Optimization of Nanoscale CMOS Inverter Using Geometric Programming by Manisha Pattanaik, Swapna Banerjee and Bikram K. Bahinipati, WSEAS Transactions on Circuits and ...
VLSI-CAD Lab electronics electrical iit kharagpur ... PhD Students Manisha Pattanaik finished her B. Tech degree (1993) in Electronics and Telecommunication at Orissa Engineering College ...
Dr. Manisha Pattanaik, AVB IIITM, Gwalior, M.P., India. Dr. M. V. Vaidyan, National Institute of Technology, Calicut, Kerala, India. Dr. Navneet Gupta, Birla Institute of ...
ABV-IIITM,Gwalior . Dr. Manisha Pattanaik Assistant Professor, ABV-IIITM,Gwalior . Secretary Dr Dileep Kumar Registrar, ABV-IIITM, Gwalior- 474 010
Dr. Manisha Pattanaik: Research & Teaching: L-6: Communication Systems Lab: C-115: 717: Dr. Aditya Trivedi: Research & Teaching: L-7: Hardware Lab: C-203: 811: Dr. Anupam Shukla
Power Delay Optimization of Nanoscale CMOS Inverter Using Geometric Programming by Manisha Pattanaik, Swapna Banerjee and Bikram K. Bahinipati, WSEAS Transactions on ...
Dr Manisha Pattanaik. 27 Curriculum design for MBA. 3 Jan 2009. Dr S Rangnekar. 20 National conference on Mathematical Modeling & Simulation . 9-11 Jan 2009
Dr Manisha Pattanaik : 812: 2449812: Dr Ritu Tiwari: 822: 2449822: Dr P. K Singh: 827: 2449827: Dr. Padmanav Acharya: 823: 2449823: Dr.K V Arya: 830: 2449830: Dr. Gaurav Agrawal
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