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PhD Student Centre for Formal Design and Verification of Software (CFDVS) Department of Computer Science and Engineering Email: seetha[@]cse[.]iitb[.]ac[.]in
S.D. Dhodapkar: [email protected]: Seetha Jayasankar: [email protected]: Simoni Shah: [email protected]: Srivathsan: [email protected]
Seetha Jayasankar: Reachability Analysis of Large Sequential Circuits : Abhisekh Sankaran: Topics in Logic and Model Theory : Ajith K. John: On Searching Very Large State Spaces for Formal ...
Seetha Jayasankar and Supratik Chakraborty. LREs: A Framework For Guiding Symbolic Reachability Analysis , Technical Report No. TR-07-23. — Technical Reports 2005-2006
Authors: Seetha Jayasankar, Supratik Chakraborty; Title: Timed Automata with Integer Resets; Authors: P. Vijay Suman, Paritosh K. Pandya, S. Krishna, Lakshmi Manasa
PhD Student Centre for Formal Design and Verification of Software (CFDVS) Department of Computer Science and Engineering Email: seetha[@]cse[.]iitb[.]ac[.]in
S.D. Dhodapkar: [email protected]: Seetha Jayasankar: [email protected]: Simoni Shah: [email protected]: Srivathsan: [email protected]
Seetha Jayasankar and Supratik Chakraborty. LREs: A Framework For Guiding Symbolic Reachability Analysis , Technical Report No. TR-07-23. Technical Reports 2005-2006
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