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Associated Lab.: Computer Design and Test Lab. (CDTL) Research Interest: VLSI Testing and Verification; Processor architecture & micro-architecture
... for Efficient Fault Tolerance in Chip Multiprocessors", Pramod Subramanyan, Virendra Singh, Kewal Saluja and Erik Larsson, Proceedings of Design ...
IEEE International Workshop on Reliability Aware System Design and Test ... Rubin Parekhji (IN) Sudhakar M. Reddy (US) Adit D. Singh (US) Virendra Singh (IN)
Sharma, Virendra Kumar, and Rai H.C. (2000): Design and simulation of H q control of switched reluctance motor, Proceedings of International Conference on Power Conversion ...
Oct. 5, 2006 virendra@BITS 3 Definitions Definitions Ñ Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. Ñ ...
Associated Lab.: Computer Design and Test Lab. (CDTL) Research Interest: VLSI Testing and Verification; Processor architecture & micro-architecture
... Fault Tolerance in Chip Multiprocessors", Pramod Subramanyan, Virendra Singh, Kewal Saluja and Erik Larsson, Proceedings of Design ...
IEEE International Workshop on Reliability Aware System Design and Test ... Rubin Parekhji (IN) Sudhakar M. Reddy (US) Adit D. Singh (US) Virendra Singh (IN)
India - --View Virendra Designer's (India) professional profile on LinkedIn. LinkedIn is the world's largest business network, helping professionals like Virendra ...
Shal Designer · Vicky/VijY Designer · Vietha01 Designer · Vijesh Designer ...
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